https://www.manualslib.com/manual/832448/Allwinner-A20.html?page=608#manual
6.4.3. UART Register List
There are 8 UART controllers. UART1 has full modem control signals, including RTS, CTS, DTR, DSR,DCD and RING signal. UART2/3 has two data flow control singals, including RTS and CTS. Other UARTcontroller has only two data signals, including DIN and DOUT. All UART controllers can be configured as Serial IrDA.
Base Address
UART0 0x01C28000 x bpi ttyS0 at MMIO 0x1c28000 (irq = 45, base_baud = 1500000) is a U6_16550A
UART1 0x01C28400
UART2 0x01C28800
UART3 0x01C28C00 x bpi ttyS1 at MMIO 0x1c28c00 (irq = 46, base_baud = 1500000) is a U6_16550A
UART4 0x01C29000
UART5 0x01C29400
UART6 0x01C29800
UART7 0x01C29C00 x bpi ttyS2 at MMIO 0x1c29c00 (irq = 47, base_baud = 1500000) is a U6_16550A
pbi m1 dmesg | grep tty
[ 3.773671] 1c28000.serial: ttyS0 at MMIO 0x1c28000 (irq = 45, base_baud = 1500000) is a U6_16550A
[ 3.773739] console [ttyS0] enabled
[ 3.797307] 1c28c00.serial: ttyS1 at MMIO 0x1c28c00 (irq = 46, base_baud = 1500000) is a U6_16550A
[ 3.820854] 1c29c00.serial: ttyS2 at MMIO 0x1c29c00 (irq = 47, base_baud = 1500000) is a U6_16550A
Register Name
UART_RBR
UART_THR
UART_DLL
UART_DLH
UART_IER
UART_IIR
UART_FCR
UART_LCR
UART_MCR
UART_LSR
UART_MSR
UART_SCH
UART_USR
UART_TFL
UART_RFL
UART_HALT
6.4.4. UART Register Description6.4.4.1.
0x00 UART Receive Buffer Register
0x00 UART Transmit Holding Register
0x00 UART Divisor Latch Low Register
0x04 UART Divisor Latch High Register
0x04 UART Interrupt Enable Register
0x08 UART Interrupt Identity Register
0x08 UART FIFO Control Register
0x0C UART Line Control Register
0x10 UART Modem Control Register
0x14 UART Line Status Register
0x18 UART Modem Status Register
0x1C UART Scratch Register
0x7C UART Status Register
0x80 UART Transmit FIFO Level
0x84 UART_RFL
0xA4 UART Halt TX Register
https://www.manualslib.com/manual/832448/Allwinner-A20.html?page=608#manual